<TABLE>
<TR  bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >inst|rst_controller|alt_rst_req_sync_uq1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|rst_controller|alt_rst_sync_uq1</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|rst_controller</TD>
<TD >33</TD>
<TD >30</TD>
<TD >0</TD>
<TD >30</TD>
<TD >2</TD>
<TD >30</TD>
<TD >30</TD>
<TD >30</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|irq_mapper</TD>
<TD >3</TD>
<TD >31</TD>
<TD >2</TD>
<TD >31</TD>
<TD >32</TD>
<TD >31</TD>
<TD >31</TD>
<TD >31</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0</TD>
<TD >38</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >37</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_004</TD>
<TD >38</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0</TD>
<TD >38</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >37</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_003</TD>
<TD >38</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0</TD>
<TD >38</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >37</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_002</TD>
<TD >38</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0</TD>
<TD >38</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >37</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter_001</TD>
<TD >38</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0</TD>
<TD >38</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >37</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|avalon_st_adapter</TD>
<TD >38</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux_001|arb|adder</TD>
<TD >8</TD>
<TD >4</TD>
<TD >0</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux_001|arb</TD>
<TD >6</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux_001</TD>
<TD >207</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >104</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux|arb|adder</TD>
<TD >20</TD>
<TD >10</TD>
<TD >0</TD>
<TD >10</TD>
<TD >10</TD>
<TD >10</TD>
<TD >10</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux|arb</TD>
<TD >9</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_mux</TD>
<TD >513</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >107</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_demux_004</TD>
<TD >106</TD>
<TD >4</TD>
<TD >2</TD>
<TD >4</TD>
<TD >205</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_demux_003</TD>
<TD >105</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >103</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_demux_002</TD>
<TD >106</TD>
<TD >4</TD>
<TD >2</TD>
<TD >4</TD>
<TD >205</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_demux_001</TD>
<TD >105</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >103</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|rsp_demux</TD>
<TD >105</TD>
<TD >1</TD>
<TD >2</TD>
<TD >1</TD>
<TD >103</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_004|arb|adder</TD>
<TD >8</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >4</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_004|arb</TD>
<TD >6</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_004</TD>
<TD >207</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >104</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_003</TD>
<TD >105</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_002|arb|adder</TD>
<TD >8</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >4</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_002|arb</TD>
<TD >6</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_002</TD>
<TD >207</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >104</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux_001</TD>
<TD >105</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_mux</TD>
<TD >105</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_demux_001</TD>
<TD >110</TD>
<TD >4</TD>
<TD >5</TD>
<TD >4</TD>
<TD >205</TD>
<TD >4</TD>
<TD >4</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cmd_demux</TD>
<TD >113</TD>
<TD >25</TD>
<TD >2</TD>
<TD >25</TD>
<TD >511</TD>
<TD >25</TD>
<TD >25</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_instruction_master_limiter</TD>
<TD >208</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >210</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_data_master_limiter</TD>
<TD >208</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >210</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_006|the_default_decode</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_006</TD>
<TD >100</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_005|the_default_decode</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_005</TD>
<TD >100</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_004|the_default_decode</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_004</TD>
<TD >100</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_003|the_default_decode</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_003</TD>
<TD >100</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_002|the_default_decode</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_002</TD>
<TD >100</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_001|the_default_decode</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router_001</TD>
<TD >100</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router|the_default_decode</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|router</TD>
<TD >100</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >103</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|onchip_ram_s1_agent_rsp_fifo</TD>
<TD >140</TD>
<TD >39</TD>
<TD >0</TD>
<TD >39</TD>
<TD >99</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|onchip_ram_s1_agent|uncompressor</TD>
<TD >34</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|onchip_ram_s1_agent</TD>
<TD >278</TD>
<TD >39</TD>
<TD >42</TD>
<TD >39</TD>
<TD >294</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|pio_0_s1_agent_rsp_fifo</TD>
<TD >140</TD>
<TD >39</TD>
<TD >0</TD>
<TD >39</TD>
<TD >99</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|pio_0_s1_agent|uncompressor</TD>
<TD >34</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|pio_0_s1_agent</TD>
<TD >278</TD>
<TD >39</TD>
<TD >42</TD>
<TD >39</TD>
<TD >294</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_debug_mem_slave_agent_rsp_fifo</TD>
<TD >140</TD>
<TD >39</TD>
<TD >0</TD>
<TD >39</TD>
<TD >99</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_debug_mem_slave_agent|uncompressor</TD>
<TD >34</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_debug_mem_slave_agent</TD>
<TD >278</TD>
<TD >39</TD>
<TD >42</TD>
<TD >39</TD>
<TD >294</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|sysid_qsys_0_control_slave_agent_rsp_fifo</TD>
<TD >140</TD>
<TD >39</TD>
<TD >0</TD>
<TD >39</TD>
<TD >99</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|sysid_qsys_0_control_slave_agent|uncompressor</TD>
<TD >34</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
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<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|sysid_qsys_0_control_slave_agent</TD>
<TD >278</TD>
<TD >39</TD>
<TD >42</TD>
<TD >39</TD>
<TD >294</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|uart_avalon_jtag_slave_agent_rsp_fifo</TD>
<TD >140</TD>
<TD >39</TD>
<TD >0</TD>
<TD >39</TD>
<TD >99</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|uart_avalon_jtag_slave_agent|uncompressor</TD>
<TD >34</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|uart_avalon_jtag_slave_agent</TD>
<TD >278</TD>
<TD >39</TD>
<TD >42</TD>
<TD >39</TD>
<TD >294</TD>
<TD >39</TD>
<TD >39</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_instruction_master_agent</TD>
<TD >166</TD>
<TD >37</TD>
<TD >71</TD>
<TD >37</TD>
<TD >132</TD>
<TD >37</TD>
<TD >37</TD>
<TD >37</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_data_master_agent</TD>
<TD >166</TD>
<TD >37</TD>
<TD >71</TD>
<TD >37</TD>
<TD >132</TD>
<TD >37</TD>
<TD >37</TD>
<TD >37</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|onchip_ram_s1_translator</TD>
<TD >101</TD>
<TD >7</TD>
<TD >4</TD>
<TD >7</TD>
<TD >87</TD>
<TD >7</TD>
<TD >7</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|pio_0_s1_translator</TD>
<TD >101</TD>
<TD >6</TD>
<TD >19</TD>
<TD >6</TD>
<TD >70</TD>
<TD >6</TD>
<TD >6</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_debug_mem_slave_translator</TD>
<TD >101</TD>
<TD >5</TD>
<TD >9</TD>
<TD >5</TD>
<TD >82</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|sysid_qsys_0_control_slave_translator</TD>
<TD >101</TD>
<TD >6</TD>
<TD >17</TD>
<TD >6</TD>
<TD >35</TD>
<TD >6</TD>
<TD >6</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|uart_avalon_jtag_slave_translator</TD>
<TD >101</TD>
<TD >5</TD>
<TD >20</TD>
<TD >5</TD>
<TD >70</TD>
<TD >5</TD>
<TD >5</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_instruction_master_translator</TD>
<TD >102</TD>
<TD >51</TD>
<TD >2</TD>
<TD >51</TD>
<TD >95</TD>
<TD >51</TD>
<TD >51</TD>
<TD >51</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|mm_interconnect_0|cpu_data_master_translator</TD>
<TD >102</TD>
<TD >12</TD>
<TD >2</TD>
<TD >12</TD>
<TD >95</TD>
<TD >12</TD>
<TD >12</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|mm_interconnect_0</TD>
<TD >240</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >242</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
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<TD >0</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram</TD>
<TD >24</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
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<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
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<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated|dpfifo</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r|rfifo|auto_generated</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_r</TD>
<TD >13</TD>
<TD >0</TD>
<TD >1</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram</TD>
<TD >24</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated|dpfifo</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
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<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w|wfifo|auto_generated</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart|the_Kernel_uart_scfifo_w</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
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<TR >
<TD >inst|uart</TD>
<TD >38</TD>
<TD >10</TD>
<TD >23</TD>
<TD >10</TD>
<TD >34</TD>
<TD >10</TD>
<TD >10</TD>
<TD >10</TD>
<TD >0</TD>
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<TR >
<TD >inst|sysid_qsys_0</TD>
<TD >3</TD>
<TD >14</TD>
<TD >2</TD>
<TD >14</TD>
<TD >32</TD>
<TD >14</TD>
<TD >14</TD>
<TD >14</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|pio_0</TD>
<TD >38</TD>
<TD >24</TD>
<TD >24</TD>
<TD >24</TD>
<TD >40</TD>
<TD >24</TD>
<TD >24</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|onchip_ram|the_altsyncram|auto_generated|mux2</TD>
<TD >65</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
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<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|onchip_ram|the_altsyncram|auto_generated|decode3</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
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<TR >
<TD >inst|onchip_ram|the_altsyncram|auto_generated</TD>
<TD >53</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
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<TD >0</TD>
<TD >0</TD>
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<TD >0</TD>
<TD >0</TD>
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<TR >
<TD >inst|onchip_ram</TD>
<TD >57</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >32</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
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<TD >0</TD>
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<TR >
<TD >inst|cpu|cpu</TD>
<TD >151</TD>
<TD >1</TD>
<TD >31</TD>
<TD >1</TD>
<TD >111</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
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<TD >0</TD>
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<TR >
<TD >inst|cpu</TD>
<TD >151</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >110</TD>
<TD >0</TD>
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<TR >
<TD >inst</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
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